The present invention relates to a chemical-mechanical polishing (CMP) slurry formulation that comprises an organometallic oxidizing agent and to a method for treating a metallic surface with the CMP slurry.
Manufacture of high performance solid state devices requires an extremely precise and clean completion of a series of unit operations. One series of unit operations refines surfaces created and manipulated in the manufacture of solid state devices. Surfaces created in the manufacture of solid state devices must meet rigid quality control criteria that include a minimizing of irregularities from one point on the surface to another. Irregularities are characterized by deviations in topography over the surfaces or by transient chemical reactions, such as an undesirable oxidation reaction on a surface. Polishing the surfaces having the irregularities is one operation used to remove the irregularities.
One polishing operation is a chemical-mechanical polishing (CMP). This polishing or "planarizing" operation produces a desired surface topography by simultaneous performance of chemical etching with an etchant and mechanical buffing with an abrasive.
The reference, Microchip Fabrication, Third Edition, by Peter van Sant (1997) generally describes the CMP operation when used to treat the surface of a silicon wafer. Specifically, Mr. van Sant described the wafers as being mounted on rotating holders and lowered onto a pad surface rotated in an opposite direction to the rotating holders. A slurry of a silica abrasive suspended in a chemical etchant such as potassium hydroxide or ammonium hydroxide is applied to the pad.
For this CMP application, the chemical etchant is typically alkaline. The alkaline pH enables a silicon wafer to form a silicone dioxide passivating layer once planarization by the etchant and silica slurry is completed. Buffing action of the pad mechanically removes the oxide continuously. This process is continued until the surface topography of each wafer is absolutely flat.
The CMP operation is the only method available for providing global planarization of an entire silicon wafer. The challenge for manufacturers utilizing the CMP operation is to employ a slurry that does not contaminate the wafer surface, that balances chemical removal from the wafer surface with abrasive aggressiveness, and that polishes the wafer at an acceptable production rate while producing a planar surface.
The CMP operation is also usable in the manufacture of an integrated circuit or a circuit section such as a metallized layer that is supported by a silicon wafer. Complex integrated circuits include multi-level metallized layers or patterns. These metallized layers are part of a dense circuit design, with a variable topography, and a material mix. This type of dense design is enhanced by planarization of the metallic components which allows precise imaging on the layers by photolithography and which reduces thinning.
One type of metallized layer is an intermetallic dielectric layer, ILD, that is comprised of an oxide, polyimide or silicon nitride. The ILD layer is etched by photomasking techniques to define circuit elements such as contact holes, and in particular, such as vias or plugs. A thin adhesion layer such as titanium nitride, TiN, is formed over the ILD and into the via hole. A conformal tungsten film is blanket deposited over the adhesion layer. The vias or plugs are also filled with tungsten. A CMP slurry and planarization method can be used in a planarization process to polish back the blanket deposited tungsten film in order to form plugs or vias within the silicon wafer.
The Cadien et al. patents, U.S. Pat. No. 5,516,346, issuing May 14, 1996, and U.S. Pat. No. 5,340,370, issuing Aug. 23, 1994, describe CMP slurries for thin films used in integrated circuit manufacturing. One embodiment of the CMP slurries described includes an oxidizing agent, potassium ferricyanide, and an abrasive such as silica. This CMP slurry is acidic and is described as having a pH within a range of 2 to 4. This CMP slurry has been used in polishing back a blanket deposited tungsten film to form plugs or vias.
The reference of Luo et al., Proc. Second International UMIC Specialty Conf on CMP, (1997) at 83, described CMP slurries for use with copper. These slurries included, as oxidizing agents, ferric nitrate and ammonium persulfate.
The Cadien et al. patent, U.S. Pat. No. 5,604,158, issuing Feb. 18, 1997, described a method of filling an opening in an insulating layer of an integrated circuit. The method includes a step of depositing a tungsten-silicide layer over the opening. Next, a tungsten layer is deposited onto the tungsten-silicide layer so that the opening is filled with tungsten. The tungsten and tungsten-silicide layers are then chemically-mechanically polished back until the insulating layer is revealed.
Monitoring the course of CMP polishing is performed by relating time of exposure of the planarized element to the CMP slurry to previous performance records for the same process circumstances. Monitoring may also be performed by assaying chemical or physical variables of the CMP slurry that are subject to change during planarization.
The Murarka et al. patent, U.S. Pat. No. 5,637,185, issuing Jun. 10, 1997, describes a system for performing chemical-mechanical planarization on a semiconductor wafer. The system includes a CMP polishing operation. The system also includes a device for measuring electrochemical potential during the CMP polishing operation.